Cache memory

Cache memory

Assignment 1

 

Task A

Cache memory has been developed to improve the performance of computer systems by reducing the memory access time. The cache memory is smaller in size but faster and makes copies of the most frequently accessed locations of the main memory. If most memory locations that are accessed are cached then the memory access time will be close to that of the cache memory.

Write an article that describes the principles behind cache memory and the three principal cache mapping functions used and summarizes their advantages and disadvantages.

Task B

Use the SMPCache software provided to carry out the following:
1. Investigate the influence of the cache size on the miss rate.

Configure a system with the following architectural characteristics:

Processors in SMP = 1.
Cache coherence protocol = MESI.
Scheme for bus arbitration = Random.
Word wide (bits) = 16.
Words by block = 16 (block size = 32 bytes).
Blocks in main memory = 8192 (main memory size = 256 KB).
Mapping = Fully-Associative.
Replacement policy = LRU.

Configure the blocks in cache using the following configurations:
1 (cache size = 0.03 KB), 2, 4, 8, 16, 32, 64, 128, 256, and 512 (cache size = 16 KB). For each of the configurations, obtain the miss rate using the traces produced by the software.

a) Draw a graph of the miss rate versus the cache size.
b) Does the miss rate increase or decrease as the cache size increases?
c) In these experiments, it may be observed that for great cache sizes, the miss rate is stabilized. Why?
d) Does the increase of cache size improve the system performance?
2. Study the influence of the block size on the miss rate.

Configure a system with the following architectural characteristics:
Processors in SMP = 1.
Cache coherence protocol = MESI.
Scheme for bus arbitration = Random.
Word wide (bits) = 16.
Main memory size = 256 KB (the number of blocks in main memory will vary).
Cache size = 4 KB (the number of blocks in cache will vary).
Mapping = Fully-Associative.
Replacement policy = LRU.

Configure the words by block using the following configurations:
4 (block size = 8 bytes), 8, 16, 32, 64, 128, 256, 512, and 1024 (block size = 2048 bytes). For each of the configurations, obtain the miss rate using the traces produced by the software.

(a) Draw a graph of the miss rate versus the cache size.
(b) Does the miss rate increase or decrease as the block size increases? Why?
(c) Does the increase of block size improve the system performance?

 

 

 

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